Mixed-Signal Digital Design (RTL) Engineer

Mixed-Signal Digital Design (RTL) Engineer required by Cork multinational to help drive the architecture, RTL design and front-end implementation of state-of-the-art mixed-signal IP such as SerDes, DDR PHYs, PLLs, ADCs, DACs and sensor interfaces.

RESPONSIBILITIES:

• As a key contributor, you’ll work in a multidisciplinary team of architects, protocol experts and algorithm developers

• Architect and implement digital sections of advanced mixed-signal IPs

• Drive RTL design using SystemVerilog with power, performance, and area (PPA) optimization

• Utilize ASIC design tools for linting, CDC, DFT, synthesis, STA, and more

• Collaborate closely with Design Verification (DV) and Physical Design (PD) teams

• Support silicon bring-up and debug alongside the test team

• Contribute to detailed design specifications and documentation

REQUIREMENTS:

• Master’s degree (or PhD/Bachelor’s with relevant experience) in Electrical Engineering, Computer Engineering, or related

• 5+ years of ASIC digital design experience with strong RTL and micro-architecture skills

• Solid understanding of ASIC front-end tools (e.g., Design Compiler, Fusion Compiler, VCS, Spyglass, Primetime)

• Excellent communication and teamwork skills in a high-performance environment

ADVANTAGEOUS:

• Expertise in low-power design methodologies

• Background in DSP, computer architecture, and algorithm optimization

• Hands-on experience with mixed-signal IP like SerDes (USB, PCIe, MIPI, UFS), DDR PHY, PLL/DLL/FLL, ADC/DAC, or sensors

• Scripting experience with Python or Perl

BENEFITS:

• Flexible hybrid work model
• Competitive salary
• Stock options
• Performance bonus
• Maternity/Paternity leave
• Relocation support
• Pension 
• Employee stock purchase scheme
• Education assistance
• Fitness and wellness benefits