Principal ASIC Digital Design Engineer

Principal ASIC Digital Design Engineer with a solid grasp of RTL design, SystemVerilog/UVM and the latest verification methodologies required by Dublin semiconductor multinational contribute to the delivery of the highest-quality silicon IP.

RESPONSIBILITIES:

• Create and execute comprehensive verification plans for complex ASICs

• Develop and maintain SystemVerilog/UVM testbenches

• Run simulations and debug RTL to ensure function and performance

• Automate verification processes to boost speed and coverage

• Collaborate with cross-functional teams to troubleshoot and optimize

• Conduct code reviews and contribute to design and verification strategy

• Analyze test results and generate detailed reports

• Drive regression testing and track coverage metrics

• Deliver robust, high-performance silicon IP for real-world applications

• Reduce time-to-market by catching issues early in development

• Improve the efficiency and scalability of verification flows

• Help build next-gen technology used in AI, automotive, IoT and more

• Be a key player in a team that drives innovation, quality and reliability

REQUIREMENTS:

• BSc or MSc in Electrical, Computer, or Communications Engineering

• 8+ years (BS) / 6+ years (MS) of ASIC digital design & verification

• Deep knowledge of SystemVerilog, UVM and object-oriented design

• Experience with simulators like VCS, NCSim or Questa

• Proficient in Python, Perl or Tcl scripting for automation

• Familiar with version control (Git, Perforce)

• Strong understanding of coverage-driven verification & formal techniques

• Working knowledge of PCIe, CXL, AMBA and other standard interfaces

• A proactive problem-solver and critical thinker

• A collaborative team player and effective communicator

• Highly organized, with the ability to juggle priorities

• Adaptable, always learning, and passionate about technology

• A detail-obsessed professional who delivers with precision