Senior ASIC Design Engineer
Job Description
Senior ASIC Design Engineer required by Cork multinational to contribute to the architecture and implementation of digital sensor subsystems. This is a unique opportunity to work on high-impact projects that shape the user experience of millions globally.
RESPONSIBILITIES:
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Architect and design digital hardware IP for sensor subsystems to be integrated into SoCs.
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Implement RTL in SystemVerilog and collaborate closely with cross-functional teams to ensure quality and performance.
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Conduct functional verification, debugging and simulation using industry-standard tools.
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Perform RTL synthesis, timing analysis and power estimation to deliver timing-closed netlists.
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Support DFT, MBIST and ECO flows throughout the design lifecycle.
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Write and maintain technical documentation and participate in regular project reviews.
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Work with software, systems and physical design teams to ensure smooth integration and system performance.
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Build and maintain Python/Tcl/Perl scripts for automation and workflow efficiency.
REQUIREMENTS:
- Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field
- 4+ years of hands-on experience in digital ASIC design, with strong RTL design skills
- Strong command of SystemVerilog, synthesis tools, and timing closure methodologies
- RTL linting and CDC tools
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Power-aware design and simulation
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Gate-level simulation and debug
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MBIST/DFT techniques
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ASIC ECO and netlist management
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Proficiency in Python, Tcl, or Perl scripting
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Excellent communication and collaboration skills
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Proven ability to thrive in fast-paced, cross-disciplinary environments
ADVANTAGEOUS:
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Technical leadership and mentoring experience is a plus
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Familiarity with SystemC/C++ and sensor subsystems is a bonus
BENEFITS:
- Flexible hybrid work model
- Competitive salary
- Stock options
- Performance bonus
- Maternity/Paternity leave
- Relocation support
- Pension
- Employee stock purchase scheme
- Education assistance
- Fitness and wellness benefits