Senior Mixed Signal Verification Engineer required in Cork by semiconductor multinational 

Responsibilities:

• Understand Analog and mixed-signal designs

• Work with spice or models to verify analog circuits with complex System Verilog (SV) based mixed-signal test benches

• Execute test plans

• Develop tests and debug test failures to fully verify mixed-signal designs

• Analyze and document simulation results, use scripting languages to improve efficiency

• Actively participate in cross functional collaboration with design teams to ensure a successful product delivery

• Work with post-Silicon teams to bring up and assist in validation testing

Requirements:

• University Degree in Electrical Engineering or similar field
• At least 5 years of professional experience in a similar role
• Solid understanding of basics of analog and digital design with ability to describe circuit behavior and functionality
• Experience in simulating circuits in spice simulators, debugging schematics, plotting and analyzing waveforms
• Demonstrated ability to read and write code in Verilog or SystemVerilog, use of digital simulators for verifying simple designs;
• Work experience with mixed-signal test benches, SVA, functional coverage, constrained randomization and UPF
• Basic knowledge of any HDL for modeling such as Verilog-AMS; SV-RNM is highly desirable, UVM knowledge is a plus
• Knowledge of C, Python, Tcl, Perl etc. for developing test content and scripts
• Knowledge of Automotive Functional safety concepts, ISO 26262 qualification experience is a plus
• Strong English written and verbal communication skills

   

Tagged as: Semiconductor